Metal gate semiconductor device and manufacturing method

ABSTRACT

A method for manufacturing a metal gate includes providing a substrate including a gate electrode located on the substrate. A plurality of layers is formed, including a first layer located on the substrate and the gate electrode and a second layer adjacent the first layer. The layers are etched to form a plurality of adjacent spacers, including a first spacer located on the substrate and adjacent the gate electrode and a second spacer adjacent the first spacer. The first spacer is then etched and a metal layer is formed on the device immediately adjacent to the gate electrode. The metal layer is then reacted with the gate electrode to form a metal gate.

BACKGROUND

This disclosure relates generally to semiconductor manufacturing, andmore particularly to a method for manufacturing a metal gate.

A gate dielectric integrity of metal-oxide-semiconductor field effecttransistor (MOSFET) is associated with reliability and lifetime ofMOSFET devices. As the gate dielectric thickness is reduced intechnology scaling-down, gate leakage is induced, increasing powerconsumption and reducing device performance.

High K materials, which include materials with K values larger thanapproximately 5, such as SiON, HfO_(x)Si_(y), or HfO₂, are implementedto realize thicker gate dielectric layers for minimized leakage currentand equivalent oxide thickness (EOT). Also, a metal gate electrode canbe used to reduce gate resistance. In addition, the metal gate can alsoreduce gate leakage that is induced by boron penetration frompolysilicon gate electrodes.

On metal gate formation, problems include many processing issues such aschemical mechanical polishing ending point detection, spacer and linerloss, and poly gate loss. On source and drain contact formation,problems include shallow trench isolation loss and spacer oxide linerloss. In general, the process involves complex steps that increase cost.

Accordingly, it would be desirable to provide an improved method formanufacturing a metal gate absent the disadvantages found in the priormethods discussed above.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view illustrating a substrate with adielectric and a gate electrode located on the substrate;

FIG. 2 is a cross sectional view illustrating an offset spacer adjacentthe gate electrode and a light doping drain implanted in the substrate;

FIG. 3 is a cross sectional view illustrating a first spacer adjacentthe gate electrode and a second spacer adjacent the first spacer;

FIG. 4 is a cross sectional view illustrating a source and a drainimplanted in the substrate;

FIG. 5 is a cross sectional view illustrating the first spacer etched sothat its top surface is substantially even with the bottom surface ofthe second spacer;

FIG. 6 is a cross sectional view illustrating a metal layer deposited onthe device and in the space left after etching the first spacer;

FIG. 7 is a cross sectional view illustrating the result of reacting themetal layer with the device to form a metal gate and a contact for thesource and the drain, and then etching the unreacted metal layer;

FIG. 8 is a cross sectional view illustrating a contact etch stop layerformed over the device;

FIG. 9 is a cross sectional view illustrating a plurality of gates madeof different materials formed on a substrate, each gate havingsubstantially the same dielectric thickness;

FIG. 10 is a cross sectional view illustrating a plurality of firstgates made of different materials formed on a substrate, each gatehaving substantially the same dielectric thickness, and a second gatemade of the same material one of the first gates formed on thesubstrate, the second gate have a dielectric thickness different thanthat of the first gates;

FIG. 11 is a cross sectional view illustrating a plurality of firstgates made of different materials formed on a substrate, each gatehaving substantially the same dielectric thickness, and a second gatemade of a different material than either one of the first gates formedon the substrate, the second gate have a dielectric thickness differentthan that of the first gates;

DETAILED DESCRIPTION

In one embodiment, a semiconductor device 100, FIG. 1, begins itsmanufacture with a substrate 102. Substrate 102 can be of a variety ofmaterials, including but not limited to bulk silicon and silicon oninsulator (SOI), SiGe, and other proper semiconductor materials. A gatedielectric 104 and a gate electrode 106 are formed on substrate 102. Thedielectric 104 can be of a variety of materials, including but notlimited to oxides and high K materials, which include materials with Kvalues larger than approximately 5, such as SiON, HfO_(x)Si_(y), orHfO₂, or a combination thereof. The gate electrode 106 may be a varietyof materials, including but not limited to polysilicon. To create thegate electrode 106 on dielectric 104 on substrate 102 configurationshown in FIG. 1, the gate electrode 106 and dielectric 104 are patternedusing conventional photolithographic and etching processing of suitablemethods known in the art. For example, one method is by patterning thesurface of underlying material with a sequential process, includingphotoresist patterning, dry etching, and photoresist stripping. Further,photoresist patterning includes processing steps of photoresist coating,softbaking, mask aligning, pattern exposing, photoresist development,and hard baking.

Once the gate electrode 106 and the dielectric 104 are formed, an offsetspacer 108, FIG. 2, is formed. Offset spacer 108 can be of a variety ofmaterials, including but not limited to oxides such as SiO₂. Offsetspacer 108 can be formed using suitable methods known in the art, suchas chemical vapor deposition followed by etching. Following theformation of offset spacer 108, an implantation may be used to formlight doping drain (LDD) 110 in substrate 102. Light doping drain 110 isoffset by a length, A, from gate electrode 106 and dielectric 104 due tooffset spacer 108. For clarity, light doping drain 110 is omitted fromsubsequent figures.

A spacer 112, FIG. 3, is then formed on the substrate 102 adjacent gateelectrode 106 and gate dielectric 104. Spacer 112 can be formed overoffset spacer 108, resulting in offset spacer becoming part of spacer112. A spacer 114 is formed adjacent spacer 112. Spacer 112 can be avariety of materials, including oxides such as SiO₂. Spacer 114 can be avariety of materials, including but not limited to SiON, Si₃N₄, SiC, ora composite made of a combination of two or more of the aforementionedmaterials. Spacer 112 and 114 can be formed using suitable methods knownin the art, such as chemical vapor deposition followed by dry etching.

Following spacer formation, a source 116, FIG. 4, and a drain 118 may beformed by doping such as implantation in substrate 102 and thenannealing device 100.

Spacer 112 is now etched, FIG. 5, removing portions of spacer 112 thatwere adjacent to gate electrode 106 and spacer 114, and forming spacer112′. In this embodiment, spacer 112 has been etched to be substantiallyeven with a bottom surface 120 of spacer 114.

A metal layer 122, FIG. 6, is then deposited on device 100. Metal layer122 may be a metal or a metal alloy, including but not limited to Ni,Co, Mo, W, Ti, Ta or other similar alloys. Metal layer 122 can bedeposited using suitable methods known in the art, such as chemicalvapor deposition or physical vapor deposition. The amount of metal layer122 deposited on device 100 must be sufficient to react with the gateelectrode 106 in order to form a metal gate.

The temperature of device 100 is then raised for a period of time, whichcauses metal layer 122 to react with gate electrode 106 to form a metalsilicide gate (“metal gate”) 106′, FIG. 7. Temperature and timerequirements will depend on the metal layer 122 and gate electrode 106used. For a Ni metal layer and a polysilicon gate electrode, atemperature of 350 C-600 C for 10 seconds to 5 minutes is sufficient toform a NiSi gate. Metal layer 122 may also react with substrate 102 toform a contact 126 for source 116 and drain 118. Then unreacted metalmay be etched away.

After formation of metal gate 106′, a layer 128, FIG. 8, is formed ondevice 100. Layer 128 can be made of a variety of materials, includingbut not limited to Si₃N₄, SiON, or a composite layer made of acombination of the aforementioned materials, and can be used as acontact etch stop layer. Layer 128 is formed using suitable methodsknown in the art, such as chemical vapor deposition.

With metal gate 106′ and layer 128 formed, FIG. 8, device 100 includesmetal gate 106′ located on substrate 102, with gate dielectric 104between metal gate 106′ and substrate 102, and spacer 112′ located onthe substrate and adjacent metal gate 106′. Spacer 114 is adjacentspacer 112′, surrounds metal gate 106′, and is spaced apart from metalgate 106′ so as to form a region 130 between metal gate 106′ and spacer114. Layer 128 is located inside region 130 and outside region 130,covering the device 100.

The metal gate manufacturing method allows gate electrodes of differentmaterials with different gate dielectric thicknesses to be formed. Thisallows high performance core devices, which can use thinner gatedielectrics to increase the performance, to be manufactured with othercore devices and input/output devices, which can use thicker gatedielectrics that reduce gate leakage. A combination of different gateelectrode materials and different gate dielectric thickness may be tunedto optimize the performance of NMOS and PMOS.

In one embodiment, FIG. 9, a substrate 200 has a gate electrode 202 anda gate electrode 204 located on its surface. Substrate 200 can be madeof a variety of materials, including but not limited to silicon orsilicon on insulator. Each gate electrode 202 and 204 has acorresponding source 116 and drain 118 in the substrate 200. Gateelectrode 202 has a dielectric 206 a located between the gate electrode202 and substrate 200. Gate electrode 204 has a dielectric 206 b locatedbetween the gate electrode 204 and substrate 200. Dielectrics 206 a and206 b can be made of a variety of materials, including but not limitedto oxides and high K materials, which include materials with K valueslarger than approximately 5, such as SiON, HfO_(x)Si_(y), or HfO₂. Forclarity spacers, contacts, and other structures on the device have beenomitted. Dielectrics 206 a and 206 b have substantially the same gatedielectric thickness H. Gate electrode 202 is made of a material A,which includes but is not limited to a variety of materials such aspolysilicon, metal, a metal alloy, a metal silicide, or a compositelayer made of a combination of two or more of the aforementionedmaterials. Gate electrode 204 is made of a material B, which isdifferent from that of material A, and includes but is not limited to avariety of materials such as polysilicon, metal, a metal alloy, a metalsilicide, or a composite layer made of a combination of two or more ofthe aforementioned materials.

In another embodiment, FIG. 10, a substrate 200 has a gate electrode202, a gate electrode 204, and a gate electrode 206 located on itssurface. Substrate 200 can be made of a variety of materials, includingbut not limited to silicon or silicon on insulator. Each gate electrode202, 204, and 206 has a corresponding source 116 and drain 118 implantedin the substrate 200. Gate electrode 202 has a dielectric 208 a locatedbetween the gate electrode 202 and substrate 200. Gate electrode 204 hasa dielectric 208 b located between the gate electrode 204 and substrate200. Gate electrode 206 has a dielectric 210 located between the gateelectrode 206 and substrate 200. Dielectrics 208 a, 208 b, and 210 canbe made of a variety of materials, including but not limited to oxidesand high K materials, which include materials with K values larger thanapproximately 5, such as SiON, HfO_(x)Si_(y), or HfO₂. For clarityspacers, contacts, and other structures on the device have been omitted.Dielectrics 208 a and 208 b have substantially the same gate dielectricthickness H. Dielectric 210 has a gate dielectric thickness I that isgreater than that of gate dielectric thickness H. Alternatively, gatedielectric thickness I may be less than that of gate dielectricthickness H. Gate electrode 202 is made of a material A, which includesbut is not limited to a variety of materials such as polysilicon, metal,a metal alloy, a metal silicide, or a composite layer made of acombination of two or more of the aforementioned materials. Gateelectrode 204 is made of a material B, which is different from that ofmaterial A, and includes but is not limited to a variety of materialssuch as polysilicon, metal, a metal alloy, a metal silicide, or acomposite layer made of a combination of two or more of theaforementioned materials. Gate electrode 206 is made of either materialA or material B.

In another embodiment, FIG. 11, a substrate 200 has a gate electrode202, a gate electrode 204, and a gate electrode 206 located on itssurface. Substrate 200 can be made of a variety of materials, includingbut not limited to silicon or silicon on insulator. Each gate electrode202, 204, and 206 has a corresponding source 116 and drain 118 implantedin the substrate 200. Gate electrode 202 has a dielectric 208 a locatedbetween the gate electrode 202 and substrate 200. Gate electrode 204 hasa dielectric 208 b located between the gate electrode 204 and substrate200. Gate electrode 206 has a dielectric 210 located between the gateelectrode 206 and substrate 200. Dielectrics 208 a, 208 b, and 210 canbe made of a variety of materials, including but not limited to oxidesand high K materials, which include materials with K values larger thanapproximately 5, such as SiON, HfO_(x)Si_(y), or HfO₂. For clarityspacers, contacts, and other structures on the device have been omitted.Dielectrics 208 a and 208 b have substantially the same gate dielectricthickness H. Dielectric 210 has a gate dielectric thickness I that isgreater than that of gate dielectric thickness H. Alternatively, gatedielectric thickness I may be less than that of gate dielectricthickness H. Gate electrode 202 is made of a material A, which includesbut is not limited to a variety of materials such as polysilicon, metal,a metal alloy, a metal silicide, or a composite layer made of acombination of two or more of the aforementioned materials. Gateelectrode 204 is made of a material B, which is different from that ofmaterial A, and includes but is not limited to a variety of materialssuch as polysilicon, metal, a metal alloy, a metal silicide, or acomposite layer made of a combination of two or more of theaforementioned materials. Gate electrode 206 is made of a material C,which is different from that of material A or B, and includes but is notlimited to a variety of materials such as polysilicon, metal, a metalalloy, a metal silicide, or a composite layer made of a combination oftwo or more of the aforementioned materials.

Although only a few exemplary embodiments of this invention have beendescribed in detail above, those skilled in the art will readilyappreciate that many modifications are possible in the exemplaryembodiments without materially departing from the novel teachings andadvantages of this invention. Accordingly, all such modifications areintended to be included within the scope of this invention as defined inthe following claims.

1. A semiconductor device comprising: a substrate; a plurality of gateelectrodes located on the substrate; a gate dielectric located betweeneach gate electrode and the substrate, the gate dielectrics beingsubstantially the same thickness; at least one of the gate electrodesmade of a first material; and at least one of the gate electrodes madeof a second material which is different from the first material.
 2. Thesemiconductor device of claim 1 wherein the substrate is silicon oninsulator.
 3. The semiconductor device of claim 1 wherein the firstmaterial is polysilicon.
 4. The semiconductor device of claim 1 whereinthe second material is selected from the group consisting of a metal, ametal alloy, a metal silicide, and a combination thereof.
 5. Thesemiconductor device of claim 1 wherein the second material includes aplurality of materials.
 6. The semiconductor device of claim 1 whereinat least one gate dielectric is an oxide.
 7. The semiconductor device ofclaim 1 wherein at least one gate dielectric is a high K material.
 8. Asemiconductor device comprising: a substrate; a plurality of first gateelectrodes located on the substrate; a first gate dielectric locatedbetween each first gate electrode and the substrate, the first gatedielectrics being substantially the same thickness; at least one of thefirst gate electrodes made of a first material; at least one of thefirst gate electrodes made of a second material which is different fromthe first material; at least one second gate electrode located on thesubstrate, the at least one second gate electrode being made of eitherthe first material or the second material; and a second gate dielectriclocated between each at least one second gate electrode and thesubstrate, the second gate dielectrics having a thickness different fromthat of the first gate dielectrics.
 9. The semiconductor device of claim8 wherein the substrate is silicon on insulator.
 10. The semiconductordevice of claim 8 wherein the first material is polysilicon.
 11. Thesemiconductor device of claim 8 wherein the second material is selectedfrom the group consisting of a metal, a metal alloy, a metal silicide,and a combination thereof.
 12. The semiconductor device of claim 8wherein the second material includes a plurality of materials.
 13. Thesemiconductor device of claim 8 wherein at least one gate dielectric isan oxide.
 14. The semiconductor device of claim 8 wherein at least onegate dielectric is a high K material.
 15. A semiconductor devicecomprising: a substrate; a plurality of first gate electrodes located onthe substrate; a first gate dielectric located between each first gateelectrode and the substrate, the first gate dielectrics beingsubstantially the same thickness; at least one of the first gateelectrodes made of a first material; at least one of the first gateelectrodes made of a second material which is different from the firstmaterial; at least one second gate electrode located on the substrate,the at least one second gate electrode being made of a third materialwhich is different from the first and second material; and a second gatedielectric located between each at least one second gate electrode andthe substrate, the second gate dielectrics having a thickness differentfrom that of the first gate dielectrics.
 16. The semiconductor device ofclaim 15 wherein the substrate is silicon on insulator.
 17. Thesemiconductor device of claim 15 wherein the first material ispolysilicon.
 18. The semiconductor device of claim 15 wherein the secondmaterial is a metal or metal alloy.
 19. The semiconductor device ofclaim 15 wherein the third material is a metal silicide.
 20. Thesemiconductor device of claim 15 further wherein the third material is aplurality of materials.
 21. The semiconductor device of claim 15 whereinat least one gate dielectric is an oxide.
 22. The semiconductor deviceof claim 15 wherein at least one gate dielectric is a high K material.23. A semiconductor device comprising: a substrate; a metal gateelectrode located on the substrate; and a plurality of spacers, theplurality of spacers including a first spacer adjacent to the metal gateelectrode and a second spacer adjacent to the first spacer.
 24. Thesemiconductor device of claim 23 wherein the metal gate electrode is ametal silicide.
 25. The semiconductor device of claim 23 wherein thefirst spacer or second spacer is selected from the group consisting ofSiON, Si₃N₄, SiC, and a combination thereof.
 26. A semiconductor devicecomprising: a substrate; a gate electrode located on the substrate; afirst spacer surrounding the gate electrode and spaced apart from thegate electrode to form a first region therebetween; and a second spacerlocated both inside and outside of the first region.
 27. Thesemiconductor device of claim 26 wherein the gate electrode is a metalsilicide.
 28. The semiconductor device of claim 26 wherein the firstspacer or second spacer is selected from the group consisting of SiON,Si₃N₄, SiC, and a combination thereof.
 29. A semiconductor devicecomprising: a substrate; a gate electrode located on the substrate; afirst spacer located on the substrate and adjacent to the gateelectrode; a second spacer located adjacent the first spacer, whichsurrounds the gate electrode and is spaced apart from the gate electrodeto form a first region therebetween; and a third spacer located bothinside and outside of the first region.
 30. The semiconductor device ofclaim 29 wherein the gate electrode is a metal silicide.
 31. Thesemiconductor device of claim 29 wherein the first spacer is SiO₂. 32.The semiconductor device of claim 29 wherein the second spacer or thirdspacer is selected from the group consisting of SiON, Si₃N₄, SiC, and acombination thereof.
 33. A method for manufacturing a metal gate on asemiconductor device comprising: providing a substrate including a gateelectrode located on the substrate; forming a plurality of layers,including a first layer located on the substrate and the gate electrodeand a second layer adjacent the first layer; etching the layers to forma plurality of adjacent spacers, including a first spacer located on thesubstrate and adjacent the gate electrode and a second spacer adjacentthe first spacer; etching the first spacer; forming a metal layer on thedevice immediately adjacent to the gate electrode; and reacting themetal layer with the gate electrode.
 34. The method of claim 33 whereinthe gate electrode is polysilicon.
 35. The method of claim 33 whereinthe first layer and first spacer are SiO₂.
 36. The method of claim 33wherein the second layer and the second spacer are Si₃N₄.
 37. The methodof claim 33 wherein the plurality of layers are formed by chemical vapordeposition.
 38. The method of claim 33 wherein the first spacer isetched so that its top surface is substantially the same height as thebottom surface of the second spacer.
 39. The method of claim 33 whereinmetal layer is Ni.
 40. The method of claim 33 wherein reacting the metallayer with the gate electrode results in a NiSi gate electrode.
 41. Themethod of claim 33 further comprising: etching the layers to expose thesubstrate; and doping the substrate to form a source and a drain. 42.The method of claim 41 further comprising: reacting the metal layer withthe substrate to form contacts for the source and the drain.
 43. Themethod of claim 33 further comprising: etching the unreacted metallayer; forming a contact etch stop layer on the device.
 44. The methodof claim 43 wherein the contact etch stop layer is selected from thegroup consisting of SiON, Si₃N₄, and a combination thereof.
 45. A methodfor manufacturing a metal gate on a semiconductor device comprising:providing a substrate including a gate electrode located on thesubstrate; forming an offset layer; etching the offset layer to form anoffset spacer adjacent to the gate electrode; forming a plurality oflayers, including a first layer located on the substrate and the gateelectrode and a second layer adjacent the first layer; etching thelayers to form a plurality of adjacent spacers, including a first spacerlocated on the substrate and adjacent the gate electrode and a secondspacer adjacent the first spacer; etching the first spacer; forming ametal layer on the device that is immediately adjacent to the gateelectrode; and reacting the metal layer with the gate electrode.
 46. Themethod of claim 45 wherein the gate electrode is polysilicon.
 47. Themethod of claim 45 wherein the first layer and first spacer are SiO₂.48. The method of claim 45 wherein the second layer and the secondspacer are Si₃N₄.
 49. The method of claim 45 wherein the plurality oflayers and the offset layer are formed by chemical vapor deposition. 50.The method of claim 45 wherein the first spacer is etched so that itstop surface is substantially the same height as the bottom surface ofthe second spacer.
 51. The method of claim 45 wherein metal layer is Ni.52. The method of claim 45 wherein reacting the metal layer with thegate electrode results in a NiSi gate electrode.
 53. The method of claim45 further comprising: etching the layers to expose the substrate; anddoping the substrate to form a source and a drain.
 54. The method ofclaim 53 further comprising: reacting the metal layer with the substrateto form contacts for the source and the drain.
 55. The method of claim45 further comprising: etching the unreacted metal layer; forming acontact etch stop layer on the device.
 56. The method of claim 55wherein the contact etch stop layer is selected from the groupconsisting of SiON, Si₃N₄, and a combination thereof.